Low-Noise Chopper-Stabilized Zero-Drift Amplifier With SAR-Assisted Automatic Offset Calibration Loop

This paper presents a low-noise chopper-stabilized zero-drift amplifier with successive approximation register (SAR)-assisted automatic offset calibration loop (AOCL). The amplifier is designed using multipath zero-drift architecture including a low frequency path (LFP) and a high frequency path (HFP). The multipath architecture can achieve the low offset, the low noise and the low drift while maintaining the wide bandwidth. The LFP amplifier exploits a chopper scheme to reduce the offset and the low-frequency noise components. The digitally assisted AOCLs in the LFP and the HFP using SAR and current-mode digital-to-analog converter (DAC) can reduce the offset coarsely. The mismatch and the offset of the LFP amplifier can generate the up-modulated output ripples. The residual ripples in the LFP can be reduced using a ripple reduction loop (RRL). To prevent secondary ripple caused by the offset of the RRL itself, an auto zero (AZ) integrator is employed. The HFP amplifier is designed using the folded-cascode structure with class-AB output stage to enhance the power efficiency. The multipath amplifier is fabricated in a 0.18 mu m CMOS process. The current consumption, supply voltage and active area are 130 mu A, 1.8 V and 0.86 mm(2) , respectively. The amplifier has a unit gain bandwidth (UGBW) of 0.875 MHz, an input referred offset of 4.6 mu V, an input referred noise of 25.6 nV/root Hz, an offset drift of 53 nV/degrees C and a noise efficiency factor (NEF) of 11.2.