3D-ISC: A 65nm 3D Compatible In-Sensor Computing Accelerator with Reconfigurable Tile Architecture for Real-Time DVS Data Compression.

A dynamic vision sensor (DVS) outputs a sequence of digital events, each representing a change in brightness at a particular time. As DVS keeps scaling down the pixel size and increasing the resolution, a larger volume of data is generated at limited bandwidth, resulting in reduced system-level throughput, as shown in Fig. 1(a). Hence, conventional interconnect solutions cannot meet the requirement of real-time data output from a high-speed DVS.