Designing a Pulse Shaper of Arbitrary Duration.

The use of features of the internal circuitry of integrated circuits (ICs), when designing pulse shapers based on transistor-transistor logic (TTL) ICs, provides the maximum steepness of the generated pulse edges with a simple circuit. At the same time, unlike other circuits, the duration of the generated pulses has almost no effect on the duration of the generated pulse edges. The duration of both the leading and trailing edges of the generated pulses is close to the minimum possible triggering time, i.e., the triggering time of one logic element. For integrated circuits of the TTL the conventional edge duration does not exceed 20 nanoseconds.