An FPGA-Based Accelerator for Graph Embedding using Sequential Training Algorithm
arxiv(2023)
摘要
A graph embedding is an emerging approach that can represent a graph
structure with a fixed-length low-dimensional vector. node2vec is a well-known
algorithm to obtain such a graph embedding by sampling neighboring nodes on a
given graph with a random walk technique. However, the original node2vec
algorithm typically relies on a batch training of graph structures; thus, it is
not suited for applications in which the graph structure changes after the
deployment. In this paper, we focus on node2vec applications for IoT (Internet
of Things) environments. To handle the changes of graph structures after the
IoT devices have been deployed in edge environments, in this paper we propose
to combine an online sequential training algorithm with node2vec. The proposed
sequentially-trainable model is implemented on an FPGA (Field-Programmable Gate
Array) device to demonstrate the benefits of our approach. The proposed FPGA
implementation achieves up to 205.25 times speedup compared to the original
model on ARM Cortex-A53 CPU. Evaluation results using dynamic graphs show that
although the accuracy is decreased in the original model, the proposed
sequential model can obtain better graph embedding that achieves a higher
accuracy even when the graph structure is changed.
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