Towards Energy-Efficient Asynchronous Circuit Design with Flip-Flop-to-Latch Replacement

With data flow controlled by handshake templates, asynchronous circuits have the potential for low power consumption and high performance. However, the control of the handshake signal introduces additional hardware overhead. We utilize latch to further reduce the power consumption, then propose an efficient design methodology for a latch-based asynchronous pipeline and timing constraints method with conventional EDA tools. An asynchronous RISC-V processor was designed and thoroughly compared with its synchronous counterpart and the popular RISC-V cores to validate the effectiveness of the proposed methodology. Experimental results demonstrate a 3.5% area optimization and a 14.9% reduction in power consumption compared with the synchronous counterpart.