Disturbance Rejection Ability Comparison for Different Solid-State Transformer Control Strategies

The conventional control of a three-stage cascaded solid-state transformer (SST) is designed assuming decoupled stages. With high-capacitance dc-link capacitors, it is possible to ignore interactions among the stages. However, in practice, when finite-size capacitance values are used, the interactions among stages are nonnegligible, potentially leading to over-voltage or under-voltage phenomena on the high-voltage dc-link capacitors. In this view, this paper compares various SST control strategies based on their disturbance rejection ability. The analysis illustrates the influence of the control variables and bandwidth chosen for each SST stage on the capacitor voltages during load transients. Small-signal analysis is provided to compare the different SST control methods. The analysis is confirmed by simulation results using PLECS.