Selective Gate Driver Encoded with a Single Digital Signal for the SiC Inverter

This paper proposed a methodology of encoding multiple levels of turn-on and turn-off gate resistances’ (R g,on and R g,off ) selections within a single digital signal in a selective gate driver (SGD) for the SiC inverter. The proposed method uses a central MCU to sense the inverter’s slowly changing variables, select the levels of R g,on and R g,off , and encode them as the time intervals of a single ePWM’s logic high and low states independent of the inverter PWM generation. One CPLD per switch follows the inverter PWM and adjusts R g,on /R g,off by decoding the single ePWM. This method achieves multiple levels of R g,on and R g,off selections, optimizes the digital channel utilization, guarantees robustness, and incurs no additional delay. The paper presents the encoder in the MCU, the methodology of encoding multi-level R g,on and R g,off selections in a single ePWM by varying its high and low states’ time intervals, and the decoder in the CPLD. The concept of the SGD encoded with a single digital signal has been verified for use in a SiC inverter.