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A183.4-nJ/Inference 152.8-Μw 35-Voice Commands Recognition Wired-Logic Processor Using Algorithm-Circuit Co-Optimization Technique

IEEE SOLID-STATE CIRCUITS LETTERS(2024)

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Abstract
A 183.4-nJ/inference single-chip wired-logic DNN processor that is capable of recognizing all 35 commands defined in the industrial standard voice recognition data set (Google speech command dataset) is developed. The algorithm-circuit co-optimized processor recognizes 3.5 times more commands with 1.6 times better-energy efficiency than the state-of-the-art analog processor while keeping design cost low. By implementing all the processing circuits and wiring required for the 16-layer DNN onto a single chip (7.63 mm(2) in 40 nm), the need to store weight coefficients and intermediate data in DRAM/SRAM is eliminated. Owing to the proposed architecture, a low-power consumption of 152.8 mu W is achieved, which is low enough for always-on applications on battery-powered IoT devices.
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Key words
Artificial neural networks,Video recording,Speech recognition,Training,Synapses,Costs,Convolution,AI processor,algorithm-circuit co-optimization,DNN,wired logic
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