Ultra-Low On-Resistance SiC LDMOS With Separated-Protected Trench Gates and Trench RESURF Technology

A novel SiC RESURF LDMOS, incorporating a trench Ptop layer and a composite structure comprising dual trench- gate and P-buried layers (PTG-TDR LDMOS), has been introduced to safeguard the gate oxide and enhance the breakdown voltage by optimizing the electric field distribution. The etched trenches within the Ptop layer, filled with a high dielectric constant medium, introduce electric field spikes at the trench corners, thereby refining the transverse electric field distribution and significantly bolstering the breakdown voltage. The trench gate reduces channel resistance, while the P-buried layer diminishes the gate oxide electric field and provides protection. The presence of both the P-buried layer and the trench Ptop layer contributes to the depletion of the Drift region, thereby increasing the doping concentration and reducing Ron,sp effectively. The results demonstrate that the proposed device achieved a remarkable breakdown voltage (BV) of 1645 V and a specific on-resistance (Ron,sp) of 2.73 mΩ·cm ² (at VGS = 15V, VDS = 5V). Consequently, Baliga's figure of merit (FOM), defined as BV ² /Ron,sp, experienced a substantial 202% improvement, reaching 991.2 MW/cm², when compared to the conventional double RESURF LDMOS.