A Near-Memory Dynamically Programmable Many-Core Overlay

Improving computational efficiency has remained a persistent challenge over the years, particularly in light of the increasing utilization of machine learning and deep learning applications in daily routines. Researchers have proposed diverse methodologies to improve processor speed; however, memory technologies have not kept pace with developments of processors. A potential solution to this disparity is found in leveraging High Bandwidth Memory (HBM), which improves memory efficiency by seamlessly integrating memory with logic on a single chip, thereby facilitating high bandwidth data transfers. In this paper, we introduce a novel architecture for a manycore processor. Through the HBM's fully independent channels, the processing elements (PEs) can execute memory transactions concurrently. The main PE in our design employs an opensource RISC-V core, which is replicated to enable parallel computation. Our proposed system, incorporating HBM, demonstrates a remarkable speed enhancement of 16x compared to a baseline configuration utilizing DDR4 memory. The effectiveness of our design is evaluated using matrix multiplication and 2D convolution benchmarks. Experimental results are generated using an Alveo U280 data accelerator card.