Hardware Accelerator of Fractional-Order Operator Based on Phase Optimized Filters With Applications

Hardware accelerators outperform CPUs in terms of performance by parallelizing the algorithm architecture and using the device's programmable resources. FPGA is a type of hardware accelerator that excels not only in performance but also in energy efficiency. So, it provides a suitable platform for implementing complicated fractional-order systems. This paper proposes a novel phase-based optimization method to implement fractional operators using FIR and IIR filters. We also compare five fractional operator implementation methods on FPGA regarding resource utilization, execution time, power, and accuracy. These methods and the proposed one are evaluated in terms of power consumption, delay, and resources to assist the designer in determining the most suitable implementation method for the given application. The proposed method has a lower phase error of 14.7% in the case of derivative operation and a lower phase error of 18.83% in the case of integration compared to the literature. In addition, the proposed methods decreased the consumed power and area by more than three times compared to the fixed-window GL fractional operator. The proposed approach implements Heaviside's inductor-terminated lossy line. In addition, it is employed as an edge detection kernel to demonstrate its effectiveness in image processing applications.