A Compact SiGe Amplifier-Frequency-Doubler Chain With 7.1-dBm $P_{\rm{sat}}$ and 98-GHz Bandwidth for Sub-THz Applications

This article presents a sub-terahertz (sub-THz) amplifier-frequency-doubler chain (AFDC) in a 130-nm SiGe process. The proposed AFDC consists of a D -band power amplifier (PA) and a J -band push–push frequency-doubler. A high common-mode rejection ratio (CMRR) of the transformers enhances the fundamental suppression of the doubler. Detailed analysis of the transformer CMRR is presented, along with a center-tap capacitor compensation method. A transformer-based wideband second-harmonic source impedance tuning method is proposed and analyzed to achieve the optimal source impedance of the doubler within a wide bandwidth, which improves the doubler output power ( $P_{\rm{out}}$ ). The impact of base voltage ( $V_{\rm{B}}$ ) on the doubler $P_{\rm{out}}$ is investigated. It is demonstrated that reducing $V_{\rm{B}}$ enhances $P_{\rm{out}}$ of the doubler when the input power is sufficiently high. The AFDC and the standalone PA are both fabricated. Under 3.3-V dc supply, measurement results of the PA exhibit a peak $S_{21}$ of 17.8 dB, a $S_{21}$ 3-dB bandwidth of 48 GHz, a maximum saturated $P_{\rm{out}}$ ( $P_{\rm{sat}}$ ) of 15.7 dBm, and a $P_{\rm{sat}}$ 3-dB bandwidth of 44 GHz. The measured AFDC exhibits a maximum $P_{\rm{sat}}$ of 7.1 dBm, a $P_{\rm{sat}}$ 3-dB bandwidth of 98 GHz, and an output fundamental suppression of over 38 dBc in the operation band. The PA and AFDC occupy extremely compact chip core areas of 0.026 and 0.066 mm $^2$ , respectively. The designed PA and AFDC are appropriate to various applications, such as D -band high-data-rate phase array transmitters, wideband local oscillator (LO) generations, and J -band measuring modules.