Loop-Tiling Based Compiling Optimization for CNN Accelerators.

With the rapid development of convolutional neural networks (CNNs), CNN accelerators have been a research focus and are continuously being developed. Loop tiling is a commonly deployed optimization method to guide hardware architecture design based on hardware resource constraints. However, the potential performance gain of loop tiling at the compiler phase is rarely considered. In this paper, a loop-tiling based compiling scheme is proposed, which could assist a large range of hardware architecture to improve the versatility and performance of inference. A network reorganization scheme is introduced which is customized to the target hardware architecture and reconstructed the network model in a more hardware-friendly manner. At the same time, the weight re-ordering is performed correspondingly to the newly generated network model to guarantee correct data access. Experimental results demonstrate that the proposed method could effectively enlarge the range of supported CNN models for CNN accelerators with various hardware configurations.