Cost-Efficient Soft Error Detection and Correction Flip-Flop Design for Nanoscale Technology.

With the rapid development of integrated circuits and the scaling down of transistor feature sizes, the susceptibility of flip-flops to the Single Event Transient (SET) and Single Event Upset (SEU) increases. In this paper, an Error Detection and Correction D Flip-Flop (EDC DFF) is proposed by radiation-hardened by design approach, which can tolerate soft errors induced by SETs and SEUs. By adding redundant detection circuits composed of a shadow latch and a detection XOR gate, and replacing the inverter at the output with the error correction circuit controlled by the error indicator signal, EDC DFF can detect and correct soft errors induced by SETs and SEUs. Compared with the existing radiation-hardened DFF designs, the EDC DFF has higher robustness, lower overhead, and the lowest APDP (Area-Power-Delay Product).