A 12-bit 50 MS/s Hybrid ADC for Waveform Sampling, Data Streaming, and Sparse Readout

This paper presents an energy-efficient 12-bit ADC in a 65 nm CMOS process for on-chip waveform digitization on multi-channel front-end ASICs. The converter uses a hybrid architecture that combines an 8-bit successive approximation register (SAR) algorithm with a 5-bit digital slope (DS) algorithm. An on-chip reference buffer with digital trimming and charge neutralization is used to minimize system-level calibration and power requirements. Simulations predict 11.0 bits of effective resolution for a full-scale input sampled at 50 MS/s while consuming 1.97 mW (including the reference buffer), resulting in a Walden figure of merit (FOM) of 19.5 fJ/bit.