Comprehensive Design Guidelines of Gate Stack for QLC and Highly Reliable Ferroelectric VNAND

Suhwan Lim, Taeyoung Kim, Ilho Myeong,Sanghyun Park, Suseong Noh,Seung Min Lee, Jongho Woo, Hanseung Ko, Youngji Noh, Moonkang Choi, Kiheun Lee,Sangwoo Han, Jongyeon Baek, Kijoon Kim,Juhyung Kim, Dongjin Jung, Kwangsoo Kim, Sijung Yoo,Hyun Jae Lee,Seung-Geol Nam, Ji-Sung Kim, Jaewoo Park, Chaeho Kim,Seunghyun Kim, Hyoseok Kim,Jinseong Heo, Kwangmin Park,Sanghun Jeon, Wanki Kim,Daewon Ha,Yu Gyun Shin,Jaihyuk Song

2023 International Electron Devices Meeting (IEDM)（2023）

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摘要

For the first time, a comprehensive guideline is proposed for a gate stack design of ferroelectric vertical NAND (Fe-VNAND), based on in-depth analytical modeling and experiments. Based on the guideline, the metal-insulator-ferroelectric (FE)-insulator-silicon (MIFIS) gate stack has been demonstrated, showcasing its benefits in all three aspects of reliability (endurance, retention, and disturb characteristics) and its potential for wide memory window (MW, 5.5 V and above), as well as compatibility for VNAND processes.

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关键词

Comprehensive Guidelines,Gate Stack,Model Analysis,Endurance,Aspects Of Reliability,Memory Window,Charge Trapping,Gate Dielectric,Band Offset,Ferroelectric Field-effect Transistor

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