Reliability-Aware Ultra-Scaled IDG-InGaZnO-FET Compact Model to Enable Cross-layer Co-design for Highly Efficient Analog Computing in 2T0C-DRAM

Ultra-scaled independent-dual-gate (IDG) InGaZnO-FET (~ 26 nm) can potentially lead to highly energy- and area-efficient computing-in-memory (CIM) structures due to its low leakage, extended operational flexibility, and capability for 3D integration. However, its complicated operation principle, increased variation sources, and enlarged parasitic effect hinder device modeling and circuit design. To address these issues, a reliability-aware compact model (RaCM) is developed to describe the surface potential with the IDG coupling effect and excellently agree with fabricated device measurements. Supported by experiments and TCAD calibrated model with variation and degradation, we firstly propose an IDG-2T0C multi-bit computing cell with diode-connected write strategy suppressing variations and independent-gate enhanced data integrity and retention schemes. Furthermore, with RaCM enabled device and circuit co-optimization, a 3D all-in-time-domain (ATD) CIM architecture is proposed. RaCM and 28-nm CMOS hybrid circuit simulation shows it achieves a normalized energy-efficiency (EF) up to 2766 TOPS/W, advancing >3× improvements over previous arts, and a CIFAR-10 inference accuracy loss < 2% after 1000s.