Modeling Degradation and Breakdown in SiO₂ and High-k Gate Dielectrics

We present a multiscale device simulation framework for modeling degradation and breakdown (BD) of gate dielectric stacks. It relies on an accurate, material-dependent description of the most relevant defect-related phenomena in dielectrics (charge trapping and transport, atomic species generation), and self-consistently models all degradation phases within the same physics-based description: stress-induced leakage current (SILC), soft (SBD), progressive (PBD) and hard breakdown (HBD). This methodology is applied to understand several key aspects related to the reliability of SiO2 and high-k (HK) gate dielectrics: i) characterization and role of defects responsible for the charge transport in fresh and stressed devices ( SILC); ii) the differences observed in the SILC behavior of nMOS and pMOS transistors; iii) the degradation of bilayer SiOx/HfO2 stacks; and iv) the voltage dependence of the time-dependent dielectric breakdown (TDDB) distribution.