Energy-efficient D-Band Power Amplifier Linearization Adopting Back-Gate Feedforward Technique in 22nm FD-SOI

This work presents a highly energy-efficient linearization technique for D-band power amplifiers (PA) in 22nm fully-depleted silicon-on-insulator (FD-SOI) technology. The nonlinear effects arising from the NMOS transistor transconductance are reduced by leveraging the back-gate terminal of the output stage devices, directly controlling the biasing point based on the input RF signal. A 2-stage PA has been designed to demonstrate the effectiveness and robustness of the proposed technique. The prototype 22nm FD-SOI CMOS PA delivers 10.2dB peak power gain, >11dBm saturated power (Psat) and a power-addedefficiency (PAE) of 6% at the 1dB output compression point (OP1dB) with an 0.8V supply centered at a carrier frequency of 150GHz. The adaptive back-gate feedforward loop improves the overall input 1dB compression point by 2.5dB while at the same time decreasing the third- and 5th-order intermodulation distortions across the entire bandwidth by 6dB and 10dB, respectively. Furthermore, the EVM is improved by 5.5 and 6.1 percentage points for a 10-MHz 5G NR 16-QAM and a 64-QAM signal, respectively.