Impact of the Threshold Dispersity Evolution on the Current Sharing of Parallel SiC MOSFETs

Parallel connection of silicon carbide (SiC) metal oxide semiconductor field effect transistors (MOSFETs) is an efficient solution for high-capacity power converters. However, a more or less dispersity of the parallel chip parameters is inevitable, which may lead to the current imbalance. Due to the existence of dynamic threshold voltage drift, the dispersity of the threshold voltage of the parallel devices during the whole life is vital for the long-term reliability. This paper aims to investigate how dispersity evolves and how it affects the current sharing. It is found that the threshold voltage dispersity indeed does not keep constant during the operation, but on the opposite, it increases with gate stress time, especially at elevated temperatures. This leads to the deterioration of the current sharing of parallel devices. A boost converter with two devices paralleled was built and tested, which validated that the threshold voltage dispersity and current imbalance ratio increase with stress time. Finally, a classification method is proposed to suppress the increase in threshold voltage dispersity and current imbalance ratio. These findings are believed to be useful to improve the performance of SiC MOSFETs in parallel applications.