Investigation on Saturation Voltage Increment of Multichip Press-Pack IGBTs Under Power Cycling Tests

In this article, the increment mechanism of the saturation voltage of multichip press-pack insulated gate bipolar transistors (IGBTs) during power cycling tests (PCTs) is investigated. Key parameters, such as the saturation voltage and the threshold voltage are monitored at several stages during the aging. The measurements show that the saturation voltage remains almost unchanged in the beginning, but it rapidly increases at the end. The maximum increment of the saturation voltage reaches 13.6% after 500K cycles. After the test, both the static parameters and the surface micromorphology of all the IGBT chips were analyzed. The chip with a higher temperature exhibits a higher saturation voltage, a higher gate leakage current, and a larger surface roughness. The average roughness has increased from 0.1 mu m (best) to nearly 1.2 mu m (worst), leading to an increment in the contact resistance of 1.5 m Omega, and a corresponding increment in the saturation voltage of 1.9%. However, gate oxide damage in the most aged chip caused the gate leakage current to increase from the nanoampere level to the milliampere level, leading to a remarkable increase in the saturation voltage until the end of the PCT.