13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5^th-Generation 10nm DRAM Process

The increasing demand for higher memory capacity has led to a greater emphasis on high-density DIMM such as 3-dimension stacked (3DS) 128GB products compared to the current mainstream 64GB DIMM. However, the adoption of 3DS-DDR5 products necessitates the use of technologies like through-silicon via (TSV), which can lead to potential drawbacks such as price escalation and additional read latency. To overcome these challenges, there exists a need to explore the development of high-capacity memory products using a monolithic die approach. Furthermore, the increasing demand for high memory capacities has also created a demand for high-speed memory interfaces. In this work, a monolithic-die-based 32Gb high-density DDR5 achieving 8Gb/s/pin is implemented. The proposed DRAM has a symmetric mosaic bank architecture, a separated DFE architecture, and an input-offset calibration system with majority voting for a high-speed receiver. Additionally, an open-close hybrid-loop DCC is used in the transmitter for high-speed operation. A 10% power reduction is achieved by this monolithic die approach, and a maximum of 1TB (8-stack) DIMM can be supported using the 3DS option.