10.8 A 281GHz, −1.5dBm Output-Power CMOS Signal Source Adopting a 46fsrms Jitter D-Band Cascaded Subharmonically Injection-Locked Sub-Sampling PLL with a 274MHz Reference

The H-band (220 to 325GHz) is gaining attention for next-generation wireless communications (B5G/6G) due to its wide data bandwidth. Among many challenging blocks for realizing H-band wireless communication links, the local oscillator (LO) is considered the most crucial building block due to its low-phase-noise (PN) and high-output-power (P out ) requirements. Poor PN is a critical limiting factor for implementing advanced modulations, such as M-QAM, in H-band transceivers [1]. High LO P out is also key to determining mixer performance. Prior works on low-PN signal sources for H-band transceivers focused on various frequency stabilization techniques [2, 3]. Recently, an H-band signal source with low PN and high P out was reported in [4] whereby a D-band (110 to 170GHz) harmonic VCO and an H-band frequency doubler were combined. In [4], the generated D-band signal is stabilized through a cascaded sub-sampling PLL (SSPLL) to reduce PN. However, the cascaded architecture led to high DC power (P DC ) and a large chip size, while the advanced modulation requirement was still not satisfied, e.g., rms jitter of less than 50fs to satisfy −30dB EVM for 64-QAM at > 100GHz.