9.3 A 71dB SNDR 200MHz BW Interleaved Pipe-SAR ADC with a Shared Residue Integrating Amplifier Achieving 173dB FoMs.

IEEE International Solid-State Circuits Conference(2024)

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摘要
Wideband (BW >100MHz) and high-dynamic-range (DR >70dB) ADCs are in high demand for next-generation wireless standards. Conventional ADC solutions face challenges in both performance and efficiency: CTDSMs demonstrate favorable DR within moderate bandwidths, but their design complexity escalates significantly when addressing wider BW due to their closed-loop nature. Conventional pipeline ADCs can achieve high BW and resolution, but this comes at the expense of high power consumption caused by the inter-stage amplifiers. The hybrid architecture of the pipe-SAR presents an appealing combination of high resolution and improved efficiency by taking advantage of the SAR architecture, which makes them well-suited for mobile devices. Nonetheless, the conversion rate of the pipe-SAR ADC remains restricted. To solve this challenge, this work presents an interleaved pipe-SAR architecture with a shared residue integrating amplifier. It improves the opamp efficiency by eliminating the reset phase in conventional residue amplifiers (RA) and provides 1 st -order noise shaping to utilize the mandatory OSR from the anti-aliasing filter. The prototype ADC achieves 71.2dB SNDR over a 200MHz BW and consumes only 12.5mW, converting to a Schreier FoM of 173.2dB.
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关键词
High-resolution,Figure Of Merit,Bias Voltage,Capacitive Coupling,Simulated Variables,Clock Cycles,Amplification Stage,Anti-aliasing Filter,Integral Gain,Performance Challenges,Switching Back
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