22.1 A 12GS/s 12b 4× Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer

2024 IEEE International Solid-State Circuits Conference (ISSCC)(2024)

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摘要
Direct RF sampling relieves the analog front-end design and delivers high system flexibility. In $\gt10 \mathrm{GS} / \mathrm{s}\gt10 \mathrm{~b}$ ADCs, time-interleaving (TI) is inescapable [1–3], while the number of channels and their front-end components should be minimized to achieve low power and adequate linearity for a wideband input. Moreover, the complexity and hardware cost associated with background calibrations of TI impairments should be minimized. However, prior calibrations face challenges to be comprehensive, which either confine the applicable input [1–3] or the accuracy [4, 5]. This work presents a global dither-injection-facilitated comprehensive calibration of TI errors (CCTI), which features an inherent input-independent characteristic like the analog calibration of [5], but more comprehensively corrects all sources of skew. The CCTI is instantiated in a 12GS/s 12b ADC in 28nm, which is only aggregated by 4 TI channels (CHs), enabling a single input buffer (IBF) with direct sampling TI front-end for high energy efficiency. The IBF works under a 1.2V supply voltage headroom and is linearized by a self-adaptive current-compensation cell (SACC-cell), accommodating $\gt65 \mathrm{~dB}$ SFDR over the Nyquist bandwidth. The ADC dissipates 179.8mW power and measures 54.1dB Nyquist SNDR, yielding 36.2fJ/conv.-step $\mathrm{FoM}_{\mathrm{w}}$ and 159.3dB $\mathrm{FoM}_{\mathrm{s}}$.
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关键词
Inverter,Slew Rate,Critical Damping
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