A 1Mb RRAM Macro With 9.8ns Read Access Time Utilizing Dynamic Reference Voltage for Reliable Sensing Operation

Resistive RAM (RRAM) has emerged as a promising candidate for the next generation of non-volatile memories (NVMs) due to its low write voltage and compact area that is compatible with CMOS technology. In this work, we propose a 1Mb macro consisting of two 512Kb sub-arrays, with the macro area reduced by implementing a common source-line (SL) structure. A voltage-mode sense amplifier (VSA) is designed to overcome the challenge of the low ratio between high-resistance and low-resistance states (R-ratio). Two columns of replica cells situated in the center of the RRAM array are used to generate the reference voltages, which exhibit behavior that closely tracks the changes in the bit-line (BL) voltage even under PVT variations. Additionally, power-gating and common-mode feedback circuits are implemented in the SA to save power and improve sensing speed. The test chip, fabricated in 40nm CMOS technology, occupies a core area of 0.996mm2. Compared to the prior work, the array density (5.58Mb/mm2) improves by 1.12×. The read access time is 9.8ns with a read precharge voltage of 0.3 V.