13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5 th -Generation 10nm DRAM Process.
IkJoon Choi, Seunghwan Hong,Kihyun Kim, Jeongsik Hwang, Seunghan Woo, Young-Sang Kim, Cheongryong Cho, Eun-Young Lee, Hun-Jae Lee,Min-Su Jung, Hee-Yun Jung, Ju-Seong Hwang, Junsub Yoon, Wonmook Lim, Hyeong-Jin Yoo, Won-Ki Lee, Jung-Kyun Oh, Dong-Su Lee,Jong-Eun Lee, Jun-Hyung Kim, Young-Kwan Kim,Su-Jin Park,Byung-Kyu Ho,Byongwook Na,Hye-In Choi, Chung-Ki Lee,Soo-Jung Lee, Hyunsung Shin,Young-Kyu Lee, Jang-Woo Ryu, Sangwoong Shin,Sungchul Park, Daihyun Lim,Seung-Jun Bae, Young-Soo Sohn,Tae-Young Oh, SangJoon Hwang IEEE International Solid-State Circuits Conference（2024）
AI 理解论文
溯源树
样例
