34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm 2 and 3.78Mb/mm 2 Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell.Hidehiro Fujiwara,Haruki Mori,Wei-Chang Zhao, Kinshuk Khare,Cheng-En Lee,Xiaochen Peng, Vineet Joshi,Chao-Kai Chuang, Shu-Huan Hsu,Takeshi Hashizume, Toshiaki Naganuma, Chen-Hung Tien,Yao-Yi Liu, Yen-Chien Lai,Chia-Fu Lee,Tan-Li Chou,Kerem Akarvardar, Saman Adham,Yih Wang,Yu-Der Chih,Yen-Huei Chen, Hung-Jen Liao,Tsung-Yung Jonathan ChangIEEE International Solid-State Circuits Conference（2024）引用 0|浏览4暂无评分AI 理解论文溯源树样例生成溯源树，研究论文发展脉络Chat Paper正在生成论文摘要
