WER: Maximizing Parallelism of Irregular Graph Applications Through GPU Warp EqualizeR

En-Ming Huang, Bo-Wun Cheng, Meng-Hsien Lin,Chun-Yi Lee,Tsung Tai Yeh

2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)(2024)

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摘要
Irregular graphs are becoming increasingly prevalent across a broad spectrum of data analysis applications. Despite their versatility, the inherent complexity and irregularity of these graphs often result in the underutilization of Single Instruction, Multiple Data (SIMD) resources when processed on Graphics Processing Units (GPUs). This underutilization originates from two primary issues: the occurrence of inactive threads and intra-warp load imbalances. These issues can produce idle threads, lead to inefficient usage of SIMD resources, consequently hamper throughput, and increase program execution time. To address these challenges, we introduce Warp EqualizeR (WER), a framework designed to optimize the utilization of SIMD resources on a GPU for processing irregular graphs. WER employs both software API and a specifically-tailored hardware microarchitecture. Such a synergistic approach enables workload redistribution in irregular graphs, which allows WER to enhance SIMD lane utilization and further harness the SIMD resources within a GPU. Our experimental results over seven different graph applications indicate that WER yields a geometric mean speedup of $2.52 \times$ and $1.47 \times$ over the baseline GPU and existing state-of-the-art methodologies, respectively.
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关键词
Graphics Processing Unit,Irregular Graph,Graph Applications,Microarchitecture,Energy Consumption,Shortest Path,Flow Control,Real-world Datasets,Betweenness Centrality,Work Motivation,Breadth-first Search,Imbalance Issue,Graph Algorithms,Graph Processing
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