Lowering of interface state density between deposited gate oxide and SiC substrate via controlling substrate oxidation

The quality of oxide/semiconductor interface in SiC gate stacks is engineered by employing atomic layer deposition of gate oxide and controlling post-deposition annealing (PDA) under the vacuum. We find that the interface state density (Dit) can be substantially lowered by reducing the thickness of thermally formed SiO2 between the deposited gate dielectric and SiC in PDA. In addition, Dit slightly far from the conduction band is further reduced by avoiding low temperature SiC oxidation and that near the conduction band is reduced by controlling suboxide formation. These results provide new insights into improving the interface performance of SiC MOS devices.