Improvement of cell transistors in high-k/metal-gate peripheral transistors technology for high-performance graphic memories

We investigated characteristics and reliabilities of cell transistors (Cell Tr) in graphics double data rate 7 (GDDR7) DRAM with high-k/metal gate (HKMG) peripheral transistors (Peri Tr), and we suggest the robust and reliable Cell Tr for the HKMG peripheral (Peri) scheme. In the latest graphic DRAMs, the HKMG Peri scheme is equipped to achieve the highest speed at the lowest power consumption, so the Cell Tr must operate stably at a lower driving voltage than other memories. Furthermore, the intrinsic properties of Cell Tr are negatively affected by the reduced thermal budget in the gate-first HKMG Peri scheme. In this paper, we propose a suitable Cell Tr to overcome the influence of the gate-first HKMG Peri scheme and the lowest driving voltage. In addition, we verify the segmental properties of node resistance in Cell Tr and the mechanism of the last data-in PRE command period (tRDL) degradation in graphic memories.