Three-dimensional numerical simulation of single event upset effect based on 55 nm DICE latch unit

With the development of nanoscale circuit technology, the on-track error rate of digital circuit and the effect of single event upset have become more pronounced. The radiation resistance research on DICE SRAM or DICE flip-flop device has been carried out extensively, including 65 nm, 90 nm, and 130 nm. However, the research on 55 nm DICE latch has not been reported. Using a three-dimensional device model of the 55 nm bulk silicon process established by the simulation tool TCAD, we verify the reinforcement performance of the DICE circuit, and clarify the effects of different incident conditions on DICE circuits. At the same time, we carry out a comparison of anti-SEU performance between NMOS transistor and PMOS transistor in the 55 nm process through comparative simulation experiments and quantitative analysis. The result shows that one of the important factors is the LET value which affects the generation rate of electron-hole pairs. A higher LET value will extend the upset recovery time of device and increase the peak of voltage. In addition, the difference in charge-sharing mechanism between transistors leads to the recovery time of PMOS higher than that of NMOS. As the angle of incidence increases, the charge-sharing mechanism between adjacent devices is enhanced, and electron-hole pairs ionized in sensitive regions increase. Due to the difference in charge mobility, the sensitivity of the angle of incidence of Nhit in DICE is much greater than that of Phit. Therefore, strict tilt angle incident test evaluation is required for DICE device before practical application. Finally, the large distance between adjacent MOS tubes will weaken the charge-sharing mechanism and reduce the charge collection of adjacent MOS tubes. Simulation result shows that the distance between the MOS transistors in the 55 nm process cannot be less than 1.2 mu m. The relevant simulation results can provide a theoretical basis and data for supporting the study of the physical mechanism of SEU and reinforcement technology, thereby promoting the application of memory devices to the aerospace field.