Built-In Self-Test of SFQ Circuits Using Side-Channel Leakage Information

Cryogenic testing and verification of single-flux quantum (SFQ) circuits consist of various challenges, such as limited number of input–output pins, flux trapping, and cooling power constraints. Developing design for testability (DFT) techniques for SFQ circuits, which address these challenges, is an important research area. In this work, a built-in self-test (BIST) methodology of SFQ circuits is proposed, which focuses on a novel way of the readout of test signals by using side-channel leakage information. The side-channel leakage can exhibit the dependence of internal data (logical “1” and “0”) on the power consumption. By measuring the variations in the power supply of an SFQ circuit at room temperature, the information about internal test signal states can be extracted with the proposed BIST methodology. As a case study, a rapid SFQ (RSFQ) 4-to-2 priority encoder circuit is considered. The existing Josephson junction (JJ)-based stuck-at fault model is applied with the proposed BIST methodology. The proposed BIST design is compared with a conventional shift register-based readout circuitry. The proposed BIST design can provide 79% lower static power consumption and 65% lower layout area. In addition, other advantages and drawbacks of the proposed design are discussed, such as yield, number of pins, testing time, interpretation of test results, and hardware security.