A transistor sizing method for standard-cell optimization considering lithography effectsJia-Syun Cai, Pin-Yuan Su,Chien-Lin Lee,Kuen-Yu TsaiDTCO and Computational Patterning III(2024)引用 0|浏览0暂无评分AI 理解论文溯源树样例生成溯源树,研究论文发展脉络Chat Paper正在生成论文摘要