A 4x32Gb/s 1.8pJ/bit Collaborative Baud-Rate CDR with Background Eye-Climbing Algorithm and Low-Power Global Clock Distribution
arxiv(2024)
摘要
This paper presents design techniques for an energy-efficient multi-lane
receiver (RX) with baud-rate clock and data recovery (CDR), which is essential
for high-throughput low-latency communication in high-performance computing
systems. The proposed low-power global clock distribution not only
significantly reduces power consumption across multi-lane RXs but is capable of
compensating for the frequency offset without any phase interpolators. To this
end, a fractional divider controlled by CDR is placed close to the global phase
locked loop. Moreover, in order to address the sub-optimal lock point of
conventional baud-rate phase detectors, the proposed CDR employs a background
eye-climbing algorithm, which optimizes the sampling phase and maximizes the
vertical eye margin (VEM). Fabricated in a 28nm CMOS process, the proposed
4x32Gb/s RX shows a low integrated fractional spur of -40.4dBc at a 2500ppm
frequency offset. Furthermore, it improves bit-error-rate performance by
increasing the VEM by 17
1.8pJ/bit with the aggregate data rate of 128Gb/s.
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