Over dV/dt Robustness of Switching Behavior of SiC MOSFET and a Novel Main Junction Region Design

In this article, the failure mechanism and improved designs of silicon carbide (SiC) metal–oxide–semiconductor field-effect transistor (MOSFET) under high dV/dt switching condition were studied. Two typical structures of the main junction region were studied, and an improved new structure was proposed. Since the space charge regions of cell, termination, and main junction were charged and discharged, respectively, the corresponding transient current will generate a transient voltage and, hence, form the additional transient electric field to the gate oxide. In the first structure, the transient electric field spike appeared at the corners of the gate oxide layer and the field oxide layer. This typical failure mode was considered to be the degradation cause of gate oxide. In the second structure, all the transient electric fields of the oxide layers, including the part at the corner between gate oxide and field oxide layer maintained at a high level, and the typical failure mode were found to be device burnout. To improve the reliability, a novel main junction structure with an isolation structure design was proposed. It could successfully inhibit the transient high electric field when the device operates at dV/dt above 100 V/ns. The TCAD simulation results validated the detailed physical mechanism and showed that the transient electric field was significantly reduced by splitting the transient currents by the proposed main junction structure.