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Flexible Real-Time Emulation of Fading Channels on SoC-FPGA Devices

2024 Panhellenic Conference on Electronics & Telecommunications (PACET)(2024)

School of Electrical and Computer Engineering

Cited 0|Views15
Abstract
Modeling and replicating the channel effects between a transmitter and receiver, is crucial in any telecommunication system, in order to evaluate the impact on the transmitted data. Therefore the necessity of having access to a real time channel emulator is vital. In order to meet these constraints, in this work we present a flexible, high performance and resource efficient FPGA-based channel emulator, focusing on fading models. Additionally, we perform a trade-off analysis between bit accuracy, resources utilization and system’s accuracy in terms of Mean Relative Error and the Probability Density Function. Our study shows that by using a circuit with reduced bit-widths, we can achieve 24%–46% reduction in various resources, while preserving the algorithmic accuracy of the channel emulator and operating at a throughput of 500Msps.
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Key words
Channel Emulation,Fading Channel,Rician,FPGA
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要点】:本文提出了一种基于SoC-FPGA的灵活、高效、资源节约的实时衰落信道模拟器,并通过权衡位精度、资源利用和系统精度,实现了显著的资源节约。

方法】:通过使用降低位宽的电路设计,保持了信道模拟器的算法精度,并进行了位精度、资源利用和系统准确度之间的权衡分析。

实验】:本文在SoC-FPGA设备上实现了衰落信道的实时模拟,并测试了在不同位宽下的资源利用和性能,结果显示在保持算法精度的情况下,实现了24%–46%的资源节约,且系统运行在500Msps的吞吐率。未提及具体使用的数据集名称。