A W-Band Power Amplifier With 19.6% PAE in 45-nm SOI CMOS

This paper presents a two-way power-combing W-band power amplifier (PA) in 45nm SOI CMOS process. To alleviate the parasitism in large-sized transistors, the customized power cell with an optimized layout is adopted. The drain-gate neutralized common-source (CS) stages are employed in the two amplification stages of the PA to enhance power gain and guarantee stability. Two types of transform-based power combining are analyzed and compared. Parallel combining is considered more suitable in this design for a lower transformation ratio and higher power-combining efficiency. The PA is designed and achieves 11.7-dBm output 1-dB compression point (P 1dB ), 15.2-dBm saturated output power (P sat ), and 19.6% power added efficiency (PAE) at 94GHz. The 3-dB bandwidth of the PA is from 85-105GHz.