A Holistic Approach for Characterization of SET Effects in a Standard Digital Cell Library.

This work introduces a framework for the gate-level characterization and modeling of Single Event Transient (SET) generation and propagation effects in CMOS standard combinational cells and their hardened variants. The characterization is based on electrical simulations, using the current pulse models for SET generation and the trapezoidal voltage pulse model for SET propagation. We have shown that by exploiting the similarities in the SET response under different input logic levels, the number of required simulations for SET generation can be reduced at least 2x. Based on obtained simulation results, the analytical models for critical charge, generated SET pulse width and propagated SET pulse width are derived. The proposed models enable to simplify the subsequent analysis of SET effects in a circuit designed with the characterized standard cells. Namely, by storing the model coefficients for each cell in the look-up table (LUT), instead of the raw data from simulations, the amount of characterization data can be reduced by at least 2 orders of magnitude, thus reducing significantly the time required to access and read the LUTs. The resulting models and the SET database are intended to serve as inputs for the soft error analysis tool.