Exploring BTI Aging Effects on Spatial Power Density and Temperature Profiles of VLSI Chips


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The Long-term reliability of a chip, encompassing factors like bias temperature instability (BTI), plays a substantial role in the chip’s operational efficiency and overall lifespan. Most studies primarily center around performance-related aspects like delay and timing impacts, and fewer studies are performed on reliability impacts on the spatial power density and thermal emerges as the predominant aging influence on CMOS devices within the sub-45nm technology nodes and beyond [1] [2].BTI arises due to the electrical field stress experienced by transistors, resulting in the generation of interface traps (caused by the rupture of Si-H bonds at the Si-SiO2 interface)profiles of chips. In this study, we propose to investigate the BTI impacts on the spatial power density and temperature profiles of VLSI chips for the first time. We assessed the BTI aging impact on the on-chip spatial power density and temperature for two widely used circuit functional blocks (dual port RAM, Discrete Cosine Transform (DCT) block) at T=130◦C and T=25◦C to account for the worst-case BTI degradation, using degradation- aware cell libraries for a 10-year aging scenario. Furthermore, we showcased the essential role of BTI aging-aware timing analysis in evaluating the impact of BTI aging on total power, on- chip spatial power density, and thermal maps. Neglecting this aspect can result in a substantial underestimation of the results related to the parameters mentioned above. We developed a power map generation method from the circuit layout and power analysis from EDA tools. We demonstrate that both circuits’ maximum power density reduction is approximately 12% and 20%, respectively. Furthermore, to analyze the BTI impact on spatial temperature, we built the heat transfer model using a multiphysics tool to imitate a real chip (Intel i7-8650U) and performed thermal simulations to evaluate the spatial thermal map. The resulting maximum temperature reduction for both these circuits is approximately 10% and 12%, respectively, which is quite significant.Our analysis has further unveiled that, in the context of a specific circuit, the position of maximum power density and the occurrence of a hot spot remains consistent over time, unaffected by aging. However, it’s important to note that these positions can vary between different circuits, primarily influenced by the workload the circuit is currently handling. Furthermore, our findings demonstrate that the effects of Bias Temperature Instability (BTI) aging are significantly more pronounced when the circuit operates at higher temperatures (T=130◦C) compared to lower operating temperatures (T= 25◦C).
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