Dielectric pocket engineered, gate induced drain leakages (GIDL) and analog performance analysis of dual metal nanowire ferroelectric MOSFET (DPE-DM-NW-Fe FET) as an inverter

This research article presents a simulation study on a dielectric pocket engineered dual metal nanowire ferroelectric (DPE-DM-NW-Fe FET) MOSFET. The aim is to mitigate the Gate-Induced Drain Leakage (GIDL) effect in the off-state condition and improve the subthreshold swing. GIDL is a type of SCE which is detrimental for the device as continuous gate leakage current. Severely hamper the performance of the device particularly in analog applications. To prevent this a novel structure is proposed in which two dielectric pockets are introduced adjacent to the source and drain to reduce the SCEs. GIDL occurs even when the gate voltage is nearly zero, but it becomes significant when the gate region is at a lower bias and the drain region is at a higher bias. The introduced dielectric pockets act as diffusion stoppers, forming insulating barriers to prevent off-state current. Simulation studies were conducted to analyze off-state GIDL currents for different channel lengths (30 nm, 40 nm, and 50 nm). Various parameters such as electric field, electron concentration, electron velocity, and surface potential have been simulated and compared with a Single Metal Gate (SMG) cylindrical MOSFET. Critical performance parameters including drain current, transconductance (gm), output conductance (gd), input capacitance (CGG), cutoff frequency (fT), gain transconductance frequency product (GTFP), gain frequency product (GFP), maximum transfer power gain (MTPG), unilateral power gain (UPG), and early voltage (Vea) have been calculated. Additionally, the noise performances of the DPE-DM-NW-Fe FET have been examined, and its implementation as a CMOS inverter have been explored for determining noise margins. The lower noise margin makes the device suitable for high-frequency applications. The simulations have been conducted using the ATLAS-3D simulator.