PARSAC: Fast, Human-quality Floorplanning for Modern SoCs with Complex Design Constraints
arxiv(2024)
摘要
The floorplanning of Systems-on-a-Chip (SoCs) and of chip sub- systems is a
crucial step in the physical design flow as it determines the optimal shapes
and locations of the blocks that make up the system. Simulated Annealing (SA)
has been the method of choice for tackling classical floorplanning problems
where the objective is to minimize wire-length and the total placement area.
The goal in industry-relevant floorplanning problems, however, is not only to
minimize area and wire-length, but to do that while respecting hard placement
constraints that specify the general area and/or the specific locations for the
placement of some blocks. We show that simply incorporating these constraints
into the SA objective function leads to sub-optimal, and often illegal,
solutions. We propose the Constraints-Aware Simulated Annealing (CA-SA) method
and show that it strongly outperforms vanilla SA in floorplanning problems with
hard placement constraints. We developed a new floorplan- ning tool on top of
CA-SA: PARSAC (Parallel Simulated Annealing with Constraints). PARSAC is an
efficient, easy-to-use, and mas- sively parallel floorplanner. Unlike current
SA-based or learning- based floorplanning tools that cannot effectively
incorporate hard placement-constraints, PARSAC can quickly construct the
Pareto- optimal legal solutions front for constrained floorplanning problems.
PARSAC also outperforms traditional SA on legacy floorplanning benchmarks.
PARSAC is available as an open-source repository for researchers to replicate
and build on our result.
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