Design and Test of a Time-to-Digital Converter ASIC Based on a Differential Delay Line

As one of the main components of a high-precision time measurement system, the Time-to-Digital Converter (TDC) is widely used in many scientific research fields. A two-stage high-precision and wide-range TDC ASIC based on a differential delay line using Delay-Locked Loop (DLL) technology is presented. The TDC ASIC consists of a coarse measurement stage for expanding the measurement range and a fine measurement stage for high-precision measurement. The coarse stage is achieved by two binary counters with dual edges sampling to avoid the metastable state. The fine stage is achieved by a Voltage-Controlled Delay Line (VCDL). The VCDL utilizes differential delay cells to mitigate the susceptibility to the power supply noise and the substrate noise. A DLL is adopted to compensate for variations in Process, Voltage and Temperature (PVT). The TDC AISC has been fabricated in a 180 nm CMOS technology and tested. A dynamic measurement range of 6.55 μs and a time resolution of 200 ps are achieved with a reference clock of 312.5 MHz. Test results show that the precision is 65.6 ps rms, the differential nonlinearity is within -0.34 LSB to 0.40 LSB.