A 10T2C Capacitive SRAM-based Computing-In-Memory Macro with Array-Embedded DAC and Shift-and-Add Functions

Capacitive SRAM-based analog computing-in-memory (A-CIM) for neural network processing has gained popularity due to its high energy efficiency and linearity in multiply-accumulate (MAC) output values [1]–[8]. On the other hand, it is widely acknowledged that the digital-to-analog converter (DAC) and analog-to-digital converter (ADC) required for processing of multi-bit input/weight (IN/w) dominate both the area and energy consumption of the entire CIM chip. To address these challenges, we propose a method for embedding DAC/shift-and-add functionality into the SRAM CIM cells to minimize the area and enhance energy efficiency (Fig. 1). Representative DAC implementation methods adopted by previous CIMs, such as selecting different input voltages from multiple voltage sources through analog switches or using resistor/capacitor ladder-based DACs, typically suffer from large area and power consumption. It is also evident that for practical execution, various on-chip low-dropout regulators not covered here are essential and inherently consume a lot of space and energy. While G. Shin et al.[7] has suggested embedding DAC functionality into the cell array, it still incurs substantial area overhead, as it needs two cells to represent a single multi-bit input. To overcome these issues, we demonstrate that DAC functionality can be implemented using only one cell with 10 transistors and 2 capacitors (10T2C), effectively reducing area and energy consumption. Additionally, conventional A-CIMs typically adopt a structure where column computing-bitline (BLc) outputs corresponding to each weight-bit position are processed independently by ADCs, followed by digital shift-and-add (S&A) operations. However, this approach increases area and energy consumption in proportion to the number of weight bits. To address this, there have been efforts to alleviate the burden imposed by ADCs by performing multi-bit S&A operations internally within the A-CIM and then processing only the results with ADC, thereby reducing the number of ADC operations. These methods, however, have limitations, as they either require the addition of capacitors to represent the bit significance of the weights on each BLc [3]–[6], or necessitate the use of additional dummy BLcs [7]. Given the area overhead challenges posed by these prior schemes, we propose an alternative structure that implements analog S&A operation within the A-CIM by adding only simple switches (SWs) without additional capacitors. Overall, the proposed scheme enables DAC and S&A operations with almost the same cell array size as previous capacitive SRAM A-CIM designs, significantly reducing the critical overhead of DAC/ADCs in A-CIM designs.