A 6.8-to-14.4GHz Octave-Tuning Fractional-N Charge-Pump PLL with Slide-Dithering-Based Background DTC Nonlinearity Calibration for Near-Integer Fractional Spur Mitigation Achieving 78fs RMS Jitter and -258.6dB $\text{FoM}_{\mathrm{T}}$.

Driven by emerging applications in wireless communication systems, the demand for fractional-N phase-locked loop (PLL) to exhibit better rms jitter, lower spurious tones and higher figure-of-merit (FoM) is becoming more and more indispensable. As the rms jitter is approaching sub-100fs, the discrete jitter contributed by the fractional spur is becoming dominant. Oigital-to-time converter (DTC) is usually used to cancel the quantization error (QE) in fractional-N PLLs so as to mitigate fractional spurs [1]. Moreover, the linearity of the DTC is of vital importance to effectively cancel the QE. However, improving the linearity of the DTC involves sacrificing its thermal noise performance. Hence, a DTC nonlinearity calibration (NLC) is urgently desired. Even though previous work has dealt with fractional spur at MHz [2], the suppression of fractional spur at kHz is still challenging due to the difficulties in extracting DTC's nonlinearity fingerprint (NLF) in near-integer fractional-N channel.