An indefinite impedance matrix technique is proposed for efficient analysis of irregular shaped planar microwave and gigabit rate printed circuit board (PCB) circuits. The proposed method combines segmentation and desegmentation algorithms in a single matrix operation. The segmentation algorithm unites multiple planar blocks to make a composite structure by connecting them at their edge ports which become dependent variables of the resulting system. The desegmentation algorithm, on the other hand, removes a planar block or multiple blocks from a structure by delimiting the removed blocks with shared ports which are dependent variables of the overarching system. Both segmentation and desegmentation algorithms require separation of ports into independent and dependent variable groups. The composite system matrix is ill-conditioned due to its dependent entries. The singularity is fixed by casting the matrix into a reduced form with the elimination of dependent entries according to proper terminal conditions. Normally, planar structures with complicated shapes can be characterized with successive application of segmentation and desegmentation methods. The proposed algorithm combines these multiple operations in a single matrix which includes the dependent ports of both added and subtracted blocks. The concomitant ill-conditioning of the augmented matrix is tackled with algebraic operations subject to terminal conditions which result in a reduced size indefinite impedance matrix. The proposed system of equations eliminate the need for successive application of segmentation and desegmentation methods and improve efficiency.
A method based on the indefinite impedance matrix application to planar circuits is developed for power delivery network (PDN) characterization of high-speed/high-density data communication circuits. By utilizing the parallel plate waveguide concept, the proposed method incorporates both ground and power via effects as well as decoupling capacitors with indefinitely many conductor layers stacked in an arbitrary order in a multilayered printed circuit board. The incorporation of analytical expressions for resonant planar circuits allows for parameterized PDN characterization and provides a significant computational advantage for a follow-up PDN optimization. The method is tested on some proof-of-concept cases and the results are observed in good agreement with those obtained from a numerical electromagnetic simulator.
Hosted Jointly by the Michigan, Ohio Valley, Ontario, Connecticut & Boston Chapters This webinar will go over the trends that are within the electronics industry that are driving the further penetration and expansion of Ruggedization technologies. These future looking trends will be supported by current real work impacts; where the lack of proper Ruggedization have led to failure. Along with an overall understanding of what Ruggedization is, why these processes are done, where these skills are used as well as the value proposition to be understood. These concepts will be further supported by a high-level review of the upstream processes that are needed as well as process controls that are empowered. About the Speaker: Jason Keeping is the Global Process Subject Matter Expert for Ruggedized Electronics within the Global Technology and Operations team at Celestica. He holds a B.A.Sc in Electrical Engineering from the University of Ryerson, is a Six Sigma/Lean Professional and a licensed professional engineer. Jason has focused his career on assessing the manufacturability and capabilities of conformal coating, potting, underfill chemistries & their interactions, dispensing technologies/processes and on assembly-level cleaning for the past twenty years. Jason is the recipient of several awards, including the 2016 SMTA Excellence in International Leadership Award, the Shingo prize for Celestica’s site in Monterrey, Mexico in 2007, and has contributed to Celestica’s Frost & Sullivan awards in 2005, 2009, 2012 & 2013. Jason is the co-chair of the IPC-HDBK-830 handbook; author for conformal coating chapter of the Printed Circuits Handbook & Lead-Free Soldering Process Development and Reliability as well was featured in the cover of Circuits Assembly in May 2008 and is currently the chair of the 5-30 Cleaning and Coating Committee within IPC and chairman overseeing the Canadian Aerospace Manufacturing Education program at Downsview Aerospace Park. Files Available to Download: Recorded Presentation (On-Demand)
