思睿逻辑

Abstract In this paper we present results on isolation of gate oxide ruptures. Samples used in this study were created using Charge Device Model (CDM) Electrostatic Discharge (ESD) stress. Electron Beam Induced Current (EBIC) technique was used to isolate the failure and visualization of the oxide rupture. This form of visual representation of the oxide rupture would be very helpful for labs with no access to TEM.

This paper presents a novel single-inductor dual-output (SIDO) DC-DC converter topology with two flying capacitors. The two flying capacitors are located in the same current path, targeting an enhanced voltage drop reduction on the inductor, and a decrease in the inductor current slope, aiming for improved power efficiency and relaxed coil current constraints. Using specifications addressing battery-powered display driver applications, simulation results show up to 7.7% efficiency improvement compared to the conventional SIDO converter and up to 4.9% efficiency improvement compared to the SIDO converter with one flying capacitor topology. In addition, a reduction in inductor peak current and ripple can be achieved, along with a lower duty cycle operation, which all lead to relaxed coil selection criteria and relaxed converter stability constraints.

Lock-in thermography (LIT) is a firmly established and powerful technique for IC defect localization. The standard approach is to detect and analyze the device temperature fluctuation between two bias conditions using an infrared thermal imaging camera and check for any anomalous heat response. For the most straightforward setup, these bias conditions would be achieved by the modulation of a supply voltage provided by the LIT system. This allows for synchronization to the internal camera frame rate. In addition to this method, the ability to provide an external trigger may be an option, as it is for the ELITE system by Thermo Fisher Scientific. This expands the LIT arena to failures that may only be observable by, for example, setting different register contents at a constant supply voltage. Though IC testers can be used to provide the stimulus and a trigger signal for these situations, often a simpler, more compact solution would be beneficial for the failure analyst. This paper presents such an alternative: the application of a low-cost, USB-based module which can emulate various communication protocols (for example, I2C, SPI) while providing a synchronized timing pulse to externally trigger the ELITE, thus facilitating dynamic LIT investigations. The efficacy of this solution is demonstrated by a case study in which dynamic LIT produced a single hot spot at the defect site that was undetected by the voltage modulation approach.

Time-Frequency transformation and spectral representations of audio signals are commonly used in various machine learning applications. Training a network on features such as the Mel-Spectrogram or Cochleogram has been proven more effective than training on time samples. In practical realizations, these are generated on a separate processor or pre-computed and stored on disk, requiring additional efforts and making it difficult to experiment with different variants. In this paper, we provide a PyTorch framework for generating the Cochleogram as well as the time-domain complex filter-banks for analysis and re-synthesis using the built-in trainable conv1d() layer. This allows computing this spectral feature on the fly as part of a larger network and enables experimenting with varying parameters. The analysis / synthesis banks enable building a trainable network that operates on complex subbands, where resynthesizing the time samples is desirable. The convolutional kernels may be trained from random values, or may be initialized and frozen or initialized and continuously trained with the rest of any network they are part of.