德州仪器

In this paper, we investigate the degradation of the thermal conductivity of diamond due to the presence of the isotope C-13. We employ a full-band Monte Carlo simulation in which phonons are modeled as semiclassical particles, and the full nonlinear phonon Boltzmann transport equation is solved. The thermal conductivity of diamond with C-13 concentrations of 0.005% (isotopically ultrapure), 0.1% (isotopically enriched), and 1.07% (naturally occurring) is computed for a temperature range of 80-500 K, showing good agreement with experimental data. The degradation of thermal conductivity with increasing isotope concentration is observed across the entire temperature range and is significant at low temperatures. At 80 K, the thermal conductivity of the naturally occurring sample is about four times lower than that of the isotopically enriched sample and eleven times lower than that of the isotopically ultrapure one. We further investigate the isotope effect on individual phonon modes and compute their individual contribution to the thermal conductivity. We also calculate the expected value of the mean free path and relaxation time of all phonon modes' population. Acoustic phonons are the principal contributors to thermal conductivity across all isotope concentrations. The optical phonon modes present relaxation times and mean free paths that are affected by the isotope concentration but are fairly constant over the entire temperature range. The acoustic phonon mean free paths decrease with increasing isotope concentration and are temperature-dependent, ranging from 2 mm to 0.5 mu m.

This paper presents an ultra-miniaturized and high-quality factor embedded loaded coaxial substrate integrated waveguide (ELCSIW) filter. Integrating a substrate-integrated coaxial resonator with a capacitively loaded air cavity achieves a 99% reduction in size compared to a conventional SIW cavity. Incorporating an air gap in the capacitive loading structure significantly enhances the resonator's quality factor. A comprehensive analysis of the miniaturization factor and quality factor in relation to cavity structure dimensions is performed. Guidelines for fabricating the highly loaded cavity are presented. To demonstrate the benefits of this technique, a two-pole band-pass filter with a 6.3% bandwidth at 1.1 GHz is designed, fabricated, and measured. The overall footprint of the filter is 10.5 mm & times; 20.5 mm, which is comparable to 0.07 lambda g & times; 0.14 lambda g. The measured insertion loss is 0.54 dB, and the upper band is spurious-free up to 7 times the resonant frequency. The exceptional performance and compactness of the loaded coaxial substrate integrated waveguide cavities highlight their immense potential for compact advanced wireless systems.

Reinforcement learning has become central to improving large reasoning models, but its success still relies heavily on verifiable rewards or labeled supervision. This limits its applicability to open ended domains where correctness is ambiguous and cannot be verified. Moreover, reasoning trajectories remain largely unconstrained, and optimization towards final answer can favor early exploitation over generalization. In this work, we ask whether general reasoning ability can be improved by teaching models how to think (the structure of reasoning) rather than what to produce (the outcome of reasoning) and extend traditional RLVR to open ended settings. We introduce structure aware reinforcement learning (SARL), a label free framework that constructs a per response Reasoning Map from intermediate thinking steps and rewards its small world topology, inspired by complex networks and the functional organization of the human brain. SARL encourages reasoning trajectories that are both locally coherent and globally efficient, shifting supervision from destination to path. Our experiments on Qwen3-4B show SARL surpasses ground truth based RL and prior label free RL baselines, achieving the best average gain of 9.1

Trans-inductor voltage regulator (TLVR) is popular nowadays to power server processors due to the better transient performance. Two types of TLVR are used commercially, one is native TLVR where the accurate channel power stage current signals is sensed and fed to VR controller. The other one is emulated TLVR, where power stage device current is emulated by an emulated current sensing scheme and fed to VR controller. However, no small-signal model exists for emulated TLVR and no design guideline has been proposed in terms of the current sensing gain and external ramp due to lack of the model. Besides, there is no knowledge for the comparison of dynamic performance between native and emulated TLVR. In this paper, a discrete-time modeling method is proposed to model both the native and emulated TLVR with constant on-time current mode control and under phase non-overlapping condition. For the first time, analytical expression of the control-to-inductor current transfer function is obtained. Based on the model, the effects of the summed current sensing gain and ramp compensation are discussed. The proposed model is verified extensively with precise SIMPLIS simulation and also real hardware experiments. Through theoretical analysis and experiment results, it reveals that compared with native TLVR, the phase margin for emulated TLVR is worse due to the effect of high order resonant poles. But with appropriate design and under phase non-overlapping condition, emulated TLVR is still an economic power solution for some server applications.

Formal verification of designs with multiple properties has been a long-standing challenge for the verification research community. The task of coming up with an effective strategy that can efficiently cluster properties to be solved together has inspired a number of proposals, ranging from structural clustering based on the property cone of influence (COI) to leverage runtime design and verification statistics. In this paper, we present an attempt towards functional clustering of properties utilizing graph neural network (GNN) embeddings for creating effective property clusters. We propose a hybrid approach that can exploit neural functional representations of hardware circuits and runtime design statistics to speed up the performance of Bounded Model Checking (BMC) in the context of multi-property verification (MPV). Our method intelligently groups properties based on their functional embedding and design statistics, resulting in speedup in verification results. Experimental results on the HWMCC benchmarks show the efficacy of our proposal with respect to the state-of-the-art.