The Government College of Engineering Poonjar (established in 2000), is an engineering institute in the state of Kerala, India. Till completion of 2014 Admissions, the college was affiliated to Cochin University of Science and Technology and currently since 2015 it is affiliated to the APJ Abdul Kalam Technological University and the courses are recognised by the All India Council for Technical Education.
Malayalam, a classical Dravidian language spoken by approximately 38 million people in the Indian state of Kerala, remains severely underrepresented in natural language processing research. This paper presents the systematic study of abstractive text summarization for Malayalam educational documents using mT5-base, a massively multilingual sequence-to-sequence transformer model. The present study employs Social-Sum-Mal, a native Malayalam dataset comprising 2,000 educational text-summary pairs derived from social studies textbooks. Three summary types available in the dataset — long summary, extreme summary, and answer summary — are analyzed separately to determine their suitability for training abstractive summarization models. The model is fine-tuned for 15 epochs with a learning rate of 1×10–4, batch size of 2 with gradient accumulation of 16 steps, on a Tesla T4 GPU. Evaluation on the test set yields ROUGE-1 of 9.81, ROUGE-2 of 2.75, ROUGE-L of 9.81, and BERT Score F1 of 88.18. Analysis reveals that long summary produces the highest inter-summary ROUGE agreement (ROUGE-1: 36.00) among the three summary types, making it the most suitable training target. The high BERT Score of 88.18 confirms that the model generates semantically accurate Malayalam summaries despite the limited training data, establishing a strong baseline for Malayalam abstractive summarization research.
A double-gate heterojunction negative-capacitance tunnel field-effect transistor is proposed for OFF-current reduction with the help of a dual-material gate. In the proposed structure, the gate oxide is a layered arrangement of high-κ dielectric over low-κ dielectric to increase gate control and to eliminate lattice mismatch issues. The tangent line approximation approach is utilized in both the source-channel region and the channel-drain region to precisely model the drain current. The model is validated using two-dimensional simulations of the double-gate heterojunction dual-material gate tunnel field-effect transistor using the one-dimensional (1-D) Landau–Khalatnikov equation. The proposed topology also exhibits improvements in sub-threshold swing, ON–OFF drain current ratio, and output characteristics. The model precisely matches the device simulator results.
The drain current improvement in a Negative Capacitance Double Gate Tunnel Field Effect Transistor (NC-DG TFET) with the help of Heterojunction (HJ) at the source-channel region is proposed and modeled in this paper. The gate oxide of the proposed TFET is a stacked configuration of high-k over low-k to improve the gate control without any lattice mismatches. Tangent Line Approximation (TLA) method is used here to model the drain current accurately. The model is validated by incorporating two dimensional simulation of DG-HJ TFET with one dimensional Landau-Khalatnikov (LK) equation. The model matches excellently with the device simulation results. The impact of stacked gate oxide topology is also studied in this paper by comparing the characteristics with unstacked gate oxide. Voltage amplification factor (A(v)), which is an important parameter in NC devices is also analyzed.
Tunnel Field Effect Transistor can be introduced as an emerging alternate to MOSFET which is energy efficient and can be used in low power applications. Due to the challenge involved in integration of band to band tunneling generation rate, the existing drain current models are inaccurate. A compact analytical model for simple tunnel FET and pnpn tunnel FET is proposed which is highly accurate. The numerical integration of tunneling generation rate in the tunneling region is performed using Simpson’s rule. Integration is done using both Simpson’s 1/3 rule and 3/8 rule and the models are validated against numerical device simulations. The models are compared with existing models and it is observed that the proposed models show excellent agreement with device simulations in the entire region of operation with Simpson’s 3/8 rule exhibiting the maximum accuracy.
A dopingless 1 transistor Dynamic Random Access Memory based on tunnel field effect transistor with dual material gate is proposed. This proposed DRAM structure shows considerable improvement in sense margin and retention time when compared with the 1T DRAM structure with double gate TFET. The current in read operation depends on the work function of source, drain and both gates. The ON current gets enhanced and OFF current becomes very low with the incorporation of dual material gate. Thus the sense margin and retention time of DRAM is improved. 2D device simulations are done with Silvaco Atlas TCAD tool. The sense margin was found out to be 31.5 nA and a retention time is 275 ms. The proposed device delivers a good trade off between sense margin and retention time. Random dopant fluctuation will not affect the performance of DRAM as it is a dopingless structure. The damages caused by ion implantation can be avoided and this makes DRAM more reliable.
