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    Model Engineering College

    72论文总数
    168引用总数

    Government Model Engineering College or MEC is an engineering college established by the IHRD, located in Thrikkakara in the South Indian state of Kerala. The college was established in 1989 and it is affiliated with the APJ Abdul Kalam Technological University.

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    机构学者

    论文(72)

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    1Recflix: A Hybrid Movie Recommendation System
    Hormis Biju Palatty, Joel Binoy Veleepalackal, Roshy James, Vyshak V Laiju, Raheena Salihin, Sony P

    This paper presents RecFlix, a multimodal movie recommendation system designed to address key limitations of traditional approaches, including data sparsity, cold-start issues, and the lack of contextual understanding of user preferences. The proposed framework effectively bridges the gap between quantitative ratings and qualitative reviews by integrating Neural Collaborative Filtering (NCF) with a Transformer Encoder to jointly model user-item interactions and extract semantic representations from textual data. A novel Gated Fusion mechanism is introduced to dynamically combine collaborative and content-based features into a unified representation. The fused features are then processed using a DeepFM-based prediction layer to capture both low- and high-order feature interactions for accurate Top-N recommendations. Experimental evaluation on a large-scale Rotten Tomatoes dataset demonstrates that RecFlix exhibits strong performance over baseline models, achieving an HR@10 of 0.6971 and an NDCG@10 of 0.4236. The results highlight the effectiveness of combining multimodal learning with adaptive feature fusion for improved ranking performance in sparse recommendation scenarios.

    20262026 3rd International Conference on Trends in Engineering Systems and Technologies (ICTEST)(2026)
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    2Dual-Image Super-Resolution for Remote Sensing Imagery Using a Modified EDSR Framework
    Roshin Jimmy, Rohit Anish, Nandu Prakash, Nikhil M, Sreekumar K

    Remote sensing image super-resolution is essential for enhancing spatial detail in Earth observation data, yet its practical deployment is constrained by the scarcity of high-resolution ground truth. This paper proposes a dual-image super-resolution framework based on a modified Enhanced Deep Super-Resolution Network (EDSR) that exploits complementary information from two low-resolution observations of the same scene. The proposed method employs a bicubic-centric dual-input strategy, where one input is obtained via bicubic down-sampling and the second via Gaussian blur followed by bicubic downsampling, reflecting realistic sensor variation in satellite imagery. A channel-fusion architecture concatenates shallow features from both inputs and passes the fused representation through a shared residual body for reconstruction. Experiments on the NWPU-RESISC45 remote sensing dataset with a 70:15:15 train/validation/test split demonstrate consistent improvement over single-image EDSR baselines, with PSNR increasing from 27.73 dB to 29.05 dB (+1.32 dB) and SSIM from 0.773 to 0.821 (+0.049). Blind evaluation on real Sentinel-2 imagery further confirms the practical applicability of the proposed framework.

    20262026 3rd International Conference on Trends in Engineering Systems and Technologies (ICTEST)(2026)
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    3Automated Segmentation and Volumetric Calculation of Haemorrhagic Stroke Using Deep Learning
    Ashlin S Biju, Angel Elsa George, Krishna Anand, Abel P S, Minimol B, Sincy P S, Kalpana George

    Intracerebral hemorrhage remains a major cause of mortality and long-term disability, making rapid neuroimaging evaluation essential for effective patient management. This study presents a cascaded deep learning framework for the automated segmentation of hemorrhagic lesions in non-contrast computed tomography scans. The architecture consists of an initial coarse segmentation stage to identify potential hemorrhage regions across axial slices, followed by a refinement stage to accurately delineate lesion boundaries within automatically generated regions of interest. To enhance feature representation, Convolutional Block Attention Modules are incorporated into the skip connections, allowing the network to emphasize important spatial and channel-wise features relevant to hemorrhage detection. The model is trained using a composite loss function, including binary cross-entropy, to address the significant class imbalance between lesion foreground and background voxels. The resulting segmentations improve the detection of small and irregular hemorrhages while maintaining accurate boundary preservation. The segmented regions are further used to estimate hemorrhage volume through voxel-based calculations using spatial metadata from NCCT images. In addition, the trained model is integrated into a lightweight web interface that enables real-time inference, visualization, case-level analysis, and automated volumetric estimation, highlighting its potential to assist clinical decision-making in neuroimaging workflows.

    20262026 3rd International Conference on Trends in Engineering Systems and Technologies (ICTEST)(2026)
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    4HDL-Based Design and Implementation of a Power-Efficient Reconfigurable LFSR
    Bhavana Krishnakumar, Anjana Devi S

    Linear Feedback Shift Registers (LFSRs) play an important role in generating test sequences for Built-In Self-Test (BIST) schemes, cryptographic applications, and Very Large Scale Integration (VLSI) testing. Conventional reconfigurable LFSRs usually have high energy dissipation due to excessive switching in inactive feedback paths. In this research, a low-power reconfigurable LFSR architecture is presented, which employs power gating based on control signals $S_{1}$ and $S_{2}$ to disable any unnecessary internal or external feedback paths. This proposed design was tested following an end-to-end process, including functional simulation in Xilinx Vivado 2024.1, hardware validation on Artix-7 Boolean board, and ASIC synthesis using Cadence Genus with the GPDK 90nm standard cell library. The complete RTL-to-GDSII physical implementation was realized in Cadence Innovus, achieving a positive slack of 561 ps and zero DRC violations. Experimental results for the 8-bit configuration demonstrate a 3.11% reduction in total power compared to conventional architectures, while maintaining a maximum operating frequency of 1.01 GHz. The proposed design offers a fabrication-ready solution optimized for high-speed, low-power BIST and VLSI testing applications.

    20262026 3rd International Conference on Trends in Engineering Systems and Technologies (ICTEST)(2026)
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    5Design and Simulation of a Dq-Controlled Cascaded H-Bridge DVR for Power Quality Enhancement in Distribution Systems
    Ali Mish Al, Thalhath P N, Thalib P M, T, Shaija P J, Asha Deepthi Vijay

    Voltage quality disturbances such as voltage sags, swells, and harmonics are major challenges in modern distribution networks, particularly in systems supplying sensitive or critical loads. Such disturbances can interrupt industrial processes, damage electronic equipment, and reduce overall system reliability. Under dynamic grid conditions, traditional mitigation techniques that use transformer-based Dynamic voltage Restorer (DVR) and two-level inverters frequently fail to provide stable compensation, low harmonic distortion, and quick response. To get around these restrictions, this paper looks into the design and simulation of a DVR based on a Cascaded H-Bridge (CHB) multilevel inverter. The three-phase voltages are transformed into the dq reference frame to enable simplified and effective control in the proposed DVR, the proposed DVR employs a discrete PID controller to regulate the injected compensating voltage. A high-resolution PWM generator produces gating signals for the CHB converter, enabling multilevel stepped voltage synthesis that reduces harmonic distortion and improves voltage waveform quality. The system incorporates DC energy storage, LC filtering, modulation circuitry, and a CHB converter to ensure effective compensation during grid disturbances. The DVR's ability to maintain balanced output across CHB cells while restoring nominal load voltage under varying sag conditions is demonstrated by MATLAB/Simulink simulations. When compared to conventional DVR architectures, the results demonstrate notable improvements in response time, voltage regulation, and harmonic performance.

    20262026 3rd International Conference on Trends in Engineering Systems and Technologies (ICTEST)(2026)
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    合作机构(25)

    APJ Abdul Kalam Technological University合作论文 6
    柯欣科技大学合作论文 5
    CMS College Kottayam合作论文 4
    俄罗斯科学院合作论文 2
    SNS College of Technology合作论文 2
    College of Engineering, Poonjar合作论文 2
    Defence Research and Development Organisation,Ministry of Defence合作论文 1
    印度理工学院古瓦哈提分校合作论文 1
    Tata Research Development and Design Centre合作论文 1
    Central Institute of Fisheries Technology,Indian Council of Agricultural Research合作论文 1

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